1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a simplified process of manufacturing a bottle-shaped deep trench capacitor for a DRAM device.
2. Description of the Prior Art
Trench-capacitor DRAM devices are known in the art. A trench-storage capacitor typically consists of a very-high-aspect-ratio contact-style hole pattern etched into the substrate, a thin storage-node dielectric insulator, a doped low-pressure chemical vapor deposition (LPCVD) polysilicon fill, and buried-plate diffusion in the substrate. The doped LPCVD silicon fill and the buried plate serve as the electrodes of the capacitor. A dielectric isolation collar in the upper region of the trench prevents leakage of the signal charge from the storage-node diffusion to the buried-plate diffusion of the capacitor. As the size of a memory cell shrinks, the chip area available for a single memory cell becomes very small. This causes reduction in capacitor area on a single chip and therefore leads to problems such as inadequate capacitance and large electrode resistance.
Various schemes are known for increasing the capacitance per unit area, for example, U.S. Pat. No. 6,448,131 filed Aug. 14, 2001, entitled “Method for Increasing the Capacitance of A Trench Capacitor”, assigned to International Business Machines Corp., discloses a method for increasing the trench capacitor surface area. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal.
U.S. Pat. No. 6,555,430 filed Nov. 28, 2000, entitled “Process Flow for Capacitance Enhancement In A DRAM Trench”, assigned to International Business Machines Corp., discloses a method including the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.
U.S. Pat. No. 6,018,174 filed Jun. 26, 1998, entitled “Bottle-Shaped Trench Capacitor With Epi Buried Layer”, assigned to Siemens Aktiengesellschaft (Munich, DE) and International Business Machines Corporation (Armonk, N.Y.), discloses a bottle-shaped trench capacitor having an expanded lower trench portion with an epi layer therein. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the expanded lower trench portion to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.
U.S. Pat. No. 6,190,988 filed May 28, 1998, by Toshiharu et al., entitled “Method for A Controlled Bottle Trench for A DRAM Storage Node”, assigned to International Business Machines Corp., discloses a bottle-shaped trench capacitor with a buried plate formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the sidewalls of the substrate with protective oxide and nitride layers. With the side walls covered, deep trench etching is then resumed, and a lower trench portion, below the protective layers of the side wall are formed. By diffusing a first dopant in the lower portion of the deep trench region, using the side wall protective layers as a mask, an etch stop is established for a wet etch process at the p/n junction established by the first dopant. The width of the lower trench portion is regulated by the time and temperature of the diffusion. Removing the doped material and applying a second dopant to the lower trench portion establishes a continuous buried plate region between trenches. A capacitor is formed by applying an insulating layer to the trench and filling with a conductor.
U.S. Pat. No. 6,365,485 filed Apr. 19, 2000, by Shiao et al., entitled “DRAM Technology of Buried Plate Formation of Bottle-Shaped Deep Trench”, assigned to Promos Tech., Inc, (TW); Mosel Vitelic Inc. (Hsinchu, TW); Siemens Ag. (Munich, DE), discloses an improved method for forming a buried plate in a bottle-shaped deep trench capacitor. The method includes the steps of: (a) forming a deep trench into a semiconductive substrate; (b) filling the deep trench with a first dielectric material to a first predetermined depth; (c) forming a silicon nitride sidewall spacer in the deep trench above the dielectric layer; (d) removing the first dielectric layer, leaving the portion of the substrate below the sidewall spacer to be exposed; (e) using the sidewall spacer as a mask, causing the exposed portion of the substrate to be oxidized, then removing the oxidized substrate; (f) forming an arsenic-ion-dope conformal layer around the side walls of the deep trench, including the sidewall spacer; (g) heating the substrate to cause the arsenic ions to diffuse into the substrate in the deep trench not covered by the sidewall spacer; and (h) removing the entire arsenic-ion-doped layer.
However, the above-mentioned prior arts have a drawback in that the process steps for making a bottle-shaped trench are too complicated, resulting in high cost and low throughput. It is often desired to simplify the semiconductor fabrication process so as to reduce the manufacturing cost.